Quote:
Originally Posted by
Klonfocius
β‘οΈ
Not in my schematics, i have 7 pages, hand drawn by Crish Hugget himself in these there is no 555, and last S/H stage (IC27) is clocked by And's (IC 37) who is in the PLL loop with two 4046's a 8253 and a Z80 CTC, defined as sync signals. The CTC counters might act as the wave readout and the 8253 are frequency deciding counters also frequency multiplicated and 4046 is the actual osc's that "ping's" the CTC!? Perhaps you have access to some other schematics?
OSCar is somewhat bizarre in design it really runs on the very edge of what the IC's can do in terms of frequency.
Sorry, it's the 4046 PLL, not a 555, it's been a while since I looked ar the schematics.
I have the same schematics (looking at them now), i also have Chris' annotated source code somewhere (very generously supplied by him when I was working on the impOSCar) and spent a while probing the hardware in various ways.
The 8253 sets the sample rate, or rather 1/32 the sample rate (the 4046 combined with the 74ls393 counter and a flipfliop in a 74lLS74 form a multiplier.
Ok, now it starts to get really clever.
This sample rate is used to clock one counter in the Z80CTC (the other oscillator the other counter), the value from this is used to read the waveform memory. as you guessed, but the clever bit is that Chris (ab)used the Z80CPU DRAM refresh cycle and line to ensure that the readout of the waveform using the CTC counter to provide the address happens when the CPU isn't going to access it. He also uses the lab of the CPU address line during that refresh cycle to select which oscillator is being updated.
The DRAM refresh stuff was a very useful feature of the Z80 put in there to make it easier and cheaper to use that processor with cheaper DRAM, but Chris didn't need it for that because he was using SRAM, so instead he found a way to make use of it that the Zilog designers almost certainly never considered, very neat.
Anyway, I digress, back to the oscillators.
If you look at sheet 4 (well sheets in my case) you see IC31 which in combination with buffers and capacitors acts as a demultiplexer and sample and hold for the output of the DAC to create control voltages, including the two oscillator volumes.
When it comes time to read an oscillator (still part of the time division multiplexing as you rightly surmised) that oscillator volume voltage is used to set the reference voltage of the DAC (so it acts as a multiplier of the oscillator volume and the waveform) and gets clocked into the sample and hold on the output of IC26
So, at this point the voltage changes at the nearest point after the CTC has updated that the TDM circuitry allows... but notice that this isn't the output.
There is one more sample and hold stage, clocked directly from the circuitry that forms the phase locked loop clocking the CTC. It is independent of the TDM logic, so the final output will actually change at precisely the point that the sample update clock ticks.
So, the oscillator is actually variable sample rate, even though TDM was used to get the voltage there ready to be output.
The oddness of the OSCar circuitry isn't down to operating frequency, everything works inside the range it was specified for, but rather because Chris is brilliantly twisted and found very neat and rather unexpected ways to achieve what he wanted in the minimum amount of circuitry. Pretty much every decision he made makes more sense when you consider he was trying to squeeze the most out of the least, for example the number and types of controls.