My DRAM theory appears to have fallen apart somewhere...
Measured all the CAS assignments today and they're broken into four groups, not the expected two.
IC45~52 are grouped, IC53~60 are grouped, IC61~68 are grouped, and IC69~72 are grouped. This follows the PCB layout exactly, as those are all grouped the same way as the ICs are physically -- when looked at in their numeric sequence, they form four (three and a half, really...) vertical columns.
IC45~48 are probably the OS DRAMs. IC45 is tied to AD0 of the LSB EPROM, and IC45 is the starting number of the DRAMs, so it makes perfect sense that it would be at the start of the memory assignment. IC46 is AD1, IC47 is AD2, and IC48 is AD3, so again, they progress logically in a physical sense, starting from the bottom of the PCB.
IC49~52 need to be puzzled out further. Since they're on the same CAS as IC45~48 then they should not be AD0, 1, 2, or 3 but the scheme isn't clear yet.
Still, it does agree with the suggested idea that the two inner most columns are DJ0~15. It seems that DK would therefore start on the right-most column at IC61 and then finish with the left-most half-column.
I was expecting something much closer to how the S950 works, but there seems to be a significant departure. Interesting.
IC88 is the Column Address Selector, so:
pin 06 - 2Y = IC45~52 (CAS0?)
pin 03 - 1Y = IC53~60 (CAS1?)
pin 11 - 4Y = IC61~68 (CAS2?)
pin 08 - 3Y = IC69~72 (CAS3?)
A/D Selectors:
IC79 - TC74HC257P
Nibble A Inputs:
pin 2 = IC49
pin 5 = IC50
pin 11 = IC51
pin 14 = IC52
Nibble B Inputs:
pin 3 = IC69
pin 6 = IC70
pin 10 = IC71
pin 13 = IC72
IC80 - TC74HC257P
Nibble A Inputs:
pin 2 = IC53
pin 5 = IC54
pin 11 = IC55
pin 14 = IC56
Nibble B Inputs:
pin 3 = IC61
pin 6 = IC62
pin 10 = IC63
pin 13 = IC64
IC81 - TC74HC257P
Nibble A Input:
pin 2 = IC57
pin 5 = IC58
pin 11 = IC59
pin 14 = IC60
Nibble B Input:
pin 3 = IC65
pin 6 = IC66
pin 10 = IC67
pin 13 = IC68
Will work on this more as time permits.
1/23/18 Update
I still believe that only the OS DRAMs are accessed by AD0~3, so the DRAM layout may be something more like this:
Work Memory is AD0~AD3 [CAS0] / Wave Group 1 is AD4~AD07 [CAS0]
Wave Group 2 is AD8~AD11 [CAS1] / Wave Group 3 is AD12~AD15 [CAS1]
Wave Group 4 is AD4~AD7 [CAS2] / Wave Group 5 is AD8~AD11 [CAS2]
Wave Group 6 is AD12~AD15 [CAS3]
Next step is to trace the DRAMs back through the TC74HC257P ICs to see their final destinations. Sad thing is--as one of the previous techs in this thread suggested--there might be no logical order of the codes to the memory layout. It could be that they're arbitrarily assigned and there will be no way to find the codes except for testing each DRAM failure one-by-one. Engineers and programmers don't tend to do strange things like that unless they're pushed by higher-ups, so I'm still going to believe there's an order to them.
1/24/18 Update
Unscrambled the data outputs from the DRAMs (74HC2257P listing above) to clearly show their groupings per nibble. It's of note that each nibble is formed by a numerically sensible grouping of 4 sequentially numbered ICs. In other words, still no real reason for the apparently scattered error codes, but it would make sense if the codes were broken into groups of 4 and then rearranged. Such as:
IC45~48 = DJ0~3 (these don't go through any multiplexing, so I think they're exactly as they appear to be)
IC49~52 = DJ4~7
IC69~72 = DJ8~11
IC53~56 = DJ12~15
IC61~64 = DK4~7
IC57~60 = DK8~11
IC65~68 = DK12~15
This seems semi-consistent with the reported error codes so far, but still off. IC 45~56 would still be DJ, although not 57~60, but don't think they actually tested one-by-one and it was just a conclusion reached by testing the first few (57~60 could easily have been skipped), so that's probably not conclusive. Also, I feel pretty confident IC65~68 is correct.
I'm wondering if the error codes reported thus far are 100% correct. I have a feeling that brute forcing the codes will come first, and then the logical pattern will present itself... working backwards.
After following the multiplexers connected to the AD lines to/from the DRAMs, they (unsurprisingly) go back to the CPU (IC1).
IC1:
pin 12 (AD4) = Y0 (pin 4) input from multiplexer IC79
pin 11 (AD5) = Y1 (pin 7)
pin 10 (AD6) = Y2 (pin 9)
pin 9 (AD7) = Y3 (pin 12)
pin 8 (AD8) = Y0 (pin 4) input from multiplexer IC80
pin 7 (AD9) = Y1 (pin 7)
pin 6 (AD10) = Y2 (pin 9)
pin 5 (AD11) = Y3 (pin 12)
pin 4 (AD12) = Y0 (pin 4) input from multiplexer IC81
pin 3 (AD13) = Y1 (pin 7)
pin 2 (AD14) = Y2 (pin 9)
pin 39 (AD15) = Y3 (pin 12)
So it looks as if AD0~3 is fed by IC45~48. AD4~7 is toggled between IC49~52 and IC69~72, AD8~11 is toggled between IC53~56 and IC61~64, and AD12~15 is toggled between IC57~60 and IC65~68.
I'm guessing that means IC49~52 + IC53~56 + IC57~60 form one 12-bit word, and IC69~72 + IC61~64 + IC65~68 form the next 12-bit word. It seems odd that it's all sequential except for IC69~72 coming ahead of IC61~68, but that might have been a board layout thing. It doesn't really matter where the data is written so long as it's read back from the same place, so maybe it was just the most convenient way to lay the traces to the multiplexer.
If so:
IC49~52 = DJ4~7
IC53~56 = DJ8~11
IC57~60 = DJ12~15
IC69~72 = DK4~7
IC61~64 = DK8~11
IC65~68 = DK12~15
This seems
really close, or correct. One of the original posters said DK07 was IC61, but I believe this was reported improperly. IC61 should in fact be DK08, as I have just tested it as a match.
I believe some of the error codes reported are because other memory errors are either being masked or unmasked. Since the RAM test cannot report multiple events, the RAM test stops on the first error reached. If there are multiple errors then the code that appears tied to a particular chip will change depending on what other chip(s) are replaced or made faulty. For example, if DK08 and DK15 are both bad, it will only report on DK08. Perhaps this phenomenon has confused things.
For the poster that was looking for DK10, I believe it is IC63. I don't know the testing order attempted in that case, but I have a feeling that (in general, if not always) low DK errors mask high DK errors, and DK errors mask DJ errors. More specifically, the check appears to run DK low to DK high and then DJ high to DJ low.
As an example, if you have a bad DK00 then every single other bad DRAM will not be detected until DK00 is repaired. If DK00 is repaired then a bad DK10 will mask DK11~15 and DJ0~15. Fix the bad DK10 and you might have a bad DJ12 which will mask DJ00~11. Repair the DJ12 and you might have a bad DJ04. Repair the bad DJ04 and hopefully your board is fixed
So... prior in the thread, someone was trying to figure out DK10. I believe they actually found DK10 and fixed it but didn't realize it because it still threw a DJ error. But... if your error is a DJ then you can assume all your DKs are okay -- at least according to my theory. If I'm correct then low DJ errors (which are not DJ0~3 or otherwise cause the OS to halt) are the best to have because it should mean most of your DRAMs are intact. If you have a low DK error then you might be replacing only one chip, or potentially quite a few.
I would suspect a great many S900 machines have bad RAM that has gone unfixed and even unnoticed -- I would even guess a large majority of S900s are not operating 100% properly. There's a huge leeway for faulty DRAMs in the S900, and you could probably have 4-5 bad chips and not even really notice depending on where it is in memory space and what is being sampled. Pretty crazy, really.